1. Technical Field
Embodiments relate to a semiconductor integrated circuit, and more particularly, to a DLL circuit of a semiconductor apparatus.
2. Related Art
In general, a DLL circuit of a semiconductor apparatus delays a reference clock to generate a DLL clock, and varies a delay time by which the reference clock is delayed, so that a phase of a feedback clock which is generated by delaying the DLL clock by as much as a predetermined time is substantially the same as that of the reference clock. At this time, if the phase of the feedback clock is substantially the same as that of the reference clock, the DLL circuit fixes the delay time to generate the DLL clock having a fixed phase. Afterwards, periodically, the DLL circuit removes the fixed delay time by which the reference clock is delayed, and varies the delay time until the phase of the feedback clock is substantially the same as that of the reference clock, and then fixes the delay time again.
In general, fixing the delay time by which the reference clock is delayed in the DLL circuit is referred to as performing a locking operation, and the locking operation is performed every time when a predetermined number of periods, e.g., three periods, of the reference clock elapses. Therefore, a period of the locking operation is substantially the same as the predetermined number of periods of the reference clock, and the period of the locking operation which is determined in such a manner cannot be changed in a circuit design.
As such, the conventional DLL circuit is configured to perform an update operation (i.e. the locking operation) every time when the predetermined number of periods of the reference clock elapses. Therefore, the conventional DLL circuit has a shorter update period as the frequency of the reference clock is increased, and has a longer update period as the frequency of the reference clock is decreased. For example, a DLL circuit configured to perform the update operation every five periods of the reference clock performs the update operation every time when ‘5X’ time elapses in a case where one period of the reference clock is ‘X’ time, whereas the DLL circuit performs the update operation every time when ‘5X−10’ time elapses in a case where one period of the reference clock is decreased to ‘X−2’ time. In other words, the conventional DLL circuit has a shorter update period as the frequency of the reference clock is increased, whereas the conventional DLL circuit has a longer update period as the frequency of the reference clock is decreased.
Therefore, if the conventional DLL circuit, due to a variation of the frequency of the reference clock, has a shorter update period than a minimum time needed to lock the DLL clock, i.e., to fix the delay time by which the reference clock is delayed, the conventional DLL circuit may not be able to perform the DLL function in a timely manner.